DeetCode.

UART Receiver FSM

Hard Verilog Protocols
Solve this problem

Design a UART receiver finite state machine (FSM) that samples serial input data at a given BAUD rate and reconstructs an 8-bit byte. The receiver must detect the start bit, sample 8 data bits LSB-first, and verify a single stop bit. The output `data_out` should contain the received byte, and `data_valid` must be asserted for exactly one clock cycle after a valid frame is received.

Constraints

  • Baud oversampling must be 16x (i.e., 16 samples per bit).
  • Frame format: 1 start bit (0), 8 data bits LSB-first, 1 stop bit (1).
  • Ignore frames with invalid start or stop bits.
  • FSM must include states for IDLE, START, DATA, STOP, and VALID.
  • Output must reset cleanly on `rst`.
  • `data_valid` must not remain asserted beyond a single clock cycle.
  • Assume synchronous active-high reset.
Starter codeVerilog
1module uart_rx (2    input wire clk,3    input wire rst,4    input wire rx,5    output reg [7:0] data_out,6    output reg data_valid7);8 9    // TODO: Implement UART Receiver FSM10    11endmodule