UART Transmitter

Hard VHDL Protocols

Design UART TX FSM in VHDL.

Constraints

Start, data, stop bits.
8 data bits.
Serial output tx.
Shift LSB-first.

Starter codeVHDL

1entity uart_tx is2  Port ( clk: in std_logic;3         rst: in std_logic;4         data: in std_logic_vector(7 downto 0);5         start: in std_logic;6         tx: out std_logic);7end uart_tx;