DeetCode.

UART TX Module

Hard Verilog Protocols
Solve this problem

Design a UART transmitter module in Verilog with configurable baud rate. It must send data serially with start/stop bits and handle busy signaling.

Constraints

  • 8 data bits, 1 start, 1 stop.
  • Configurable baud divider.
  • tx_busy asserted while sending.
  • tx line idles high.
  • synchronous FSM.
Starter codeVerilog
1module uart_tx(2    input wire clk,3    input wire rst,4    input wire [7:0] data,5    input wire send,6    output reg tx,7    output reg busy8);9// TODO10endmodule