DeetCode.

Watchdog Timer Module

Medium Verilog Reliability Asked at Bosch
Solve this problem

Design a hardware watchdog that asserts a reset request if it is not kicked within a programmable timeout, and that cannot be disabled once enabled.

Constraints

  • Timeout is loaded from a register.
  • A kick reloads the counter.
  • reset_req asserts and latches when the counter reaches zero.
  • Once enabled, the enable bit ignores further writes.
  • Only a system reset clears reset_req.
  • The timeout register cannot be changed while enabled.
Starter codeVerilog
1module watchdog (2    input wire clk,3    input wire rst,4    input wire enable_wr,5    input wire timeout_wr,6    input wire [15:0] timeout_val,7    input wire kick,8    output reg reset_req9);10// TODO11endmodule